
147
XMEGA A [MANUAL]
8077I–AVR–11/2012
Bits 3:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero
when this register is written.
Bit 1:0 – CLKOUT[1:0]: Clock Output Port
These bits decide which port the peripheral clock will be output to. Pin 7 on the selected port is the default used. The
CLKOUT setting will override the EVOUT setting. Thus, if both are enabled on the same port pin, the peripheral clock will
be visible. The port pin must be configured as output for the clock to be available on the pin.
13.15 Register Descriptions – Virtual Port
13.15.1 DIR – Data Direction register
Bit 7:0 – DIR[7:0]: Data Direction
This register sets the data direction for the individual pins in the port mapped by VPCTRLA, virtual port-map control
register A or VPCTRLB, virtual port-map control register B. When a port is mapped as virtual, accessing this register is
identical to accessing the actual DIR register for the port.
Table 13-8. Event output pin selection.
EVOUT[1:0]
Group configuration
Description
00
OFF
Event output disabled
01
PC
Event channel 0 output on PORTC
10
PD
Event channel 0 output on PORTD
11
PE
Event channel 0 output on PORTE
Table 13-9. Clock output port configurations.
CLKOUT[1:0]
Group configuration
Description
00
OFF
Clock output disabled
01
PC
Clock output on PORTC
10
PD
Clock output on PORTD
11
PE
Clock output on PORTE
Bit
7
6
543
210
+0x00
DIR[7:0]
Read/Write
R/W
Initial Value
0